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1 features ? single voltage operation C 5v read C 5v reprogramming ? fast read access time - 90 ns ? internal program control and timer ? 8k bytes boot block with lockout ? fast erase cycle time - 10 seconds ? byte-by-byte programming - 50 s/byte ? hardware data protection ? data polling for end of program detection ? low power dissipation C 50 ma active current C 100 a cmos standby current ? typical 10,000 write cycles description the at49f020 is a 5-volt only in-system flash memory. its 2 megabits of memory is organized as 262,144 words by 8 bits. manufactured with atmels advanced nonvola- tile cmos technology, the device offers access times to 90 ns with power dissipation of just 275 mw over the commercial temperature range. when the device is dese- lected, the cmos standby current is less than 100 m a. to allow for simple in-system reprogrammability, the at49f020 does not require high input voltages for programming. five-volt-only commands determine the read and programming operation of the device. reading data out of the device is similar to reading from an eprom. reprogramming the at49f020 is performed by erasing the entire 2 megabits of memory and then programming on a byte by byte basis. the byte 2-megabit (256k x 8) 5-volt only flash memory at49f020 rev. 0567cC10/98 pin configurations pin name function a0 - a17 addresses ce chip enable oe output enable we write enable i/o0 - i/o7 data inputs/outputs nc no connect tsop top view type 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a11 a9 a8 a13 a14 a17 we vcc nc a16 a15 a12 a7 a6 a5 a4 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 gnd i/o2 i/o1 i/o0 a0 a1 a2 a3 dip top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 nc a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 gnd vcc we a17 a14 a13 a8 a9 a11 oe a10 ce i/o7 i/o6 i/o5 i/o4 i/o3 (continued) plcc top view 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 a14 a13 a8 a9 a11 oe a10 ce i/o7 4 3 2 1 32 31 30 14 15 16 17 18 19 20 i/o1 i/o2 gnd i/o3 i/o4 i/o5 i/o6 a12 a15 a16 nc vcc we a17
at49f020 2 programming time is a fast 50 m s. the end of a program cycle can be optionally detected by the data polling fea- ture. once the end of a byte program cycle has been detected, a new access for a read or program can begin. the typical number of program and erase cycles is in excess of 10,000 cycles. the optional 8k bytes boot block section includes a repro- gramming write lock out feature to provide data integrity. the boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is perma- nently protected from being reprogrammed. block diagram device operation read: the at49f020 is accessed like an eprom. when ce and oe are low and we is high, the data stored at the memory location determined by the address pins is asserted on the outputs. the outputs are put in the high impedance state whenever ce or oe is high. this dual-line control gives designers flexibility in preventing bus conten- tion. erasure: before a byte can be reprogrammed, the 256k bytes memory array (or 248k bytes if the boot block fea- tured is used) must be erased. the erased state of the memory bits is a logical 1. the entire device can be erased at one time by using a 6-byte software code. the software chip erase code consists of 6-byte load com- mands to specific address locations with a specific data pattern (please refer to the chip erase cycle waveforms). after the software chip erase has been initiated, the device will internally time the erase operation so that no external clocks are required. the maximum time needed to erase the whole chip is t ec . if the boot block lockout feature has been enabled, the data in the boot sector will not be erased. byte programming: once the memory array is erased, the device is programmed (to a logical 0) on a byte-by-byte basis. please note that a data 0 cannot be programmed back to a 1; only erase operations can con- vert 0s to 1s. programming is accomplished via the internal device command register and is a 4 bus cycle operation (please refer to the command definitions table). the device will automatically generate the required internal program pulses. the program cycle has addresses latched on the falling edge of we or ce , whichever occurs last, and the data latched on the rising edge of we or ce , whichever occurs first. programming is completed after the specified t bp cycle time. the data polling feature may also be used to indi- cate the end of a program cycle. boot block programming lockout: the device has one designated block that has a programming lockout feature. this feature prevents programming of data in the designated block once the feature has been enabled. the size of the block is 8k bytes. this block, referred to as the boot block, can contain secure code that is used to bring up the system. enabling the lockout feature will allow the boot code to stay in the device while data in the rest of the device is updated. this feature does not have to be acti- vated; the boot blocks usage as a write protected region is optional to the user. the address range of the boot block is 00000h to 01fffh. once the feature is enabled, the data in the boot block can no longer be erased or programmed. data in the main memory block can still be changed through the regular pro- gramming method. to activate the lockout feature, a series of six program commands to specific addresses with spe- cific data must be performed. please refer to the command definitions table. boot block lockout detection: a software method is available to determine if programming of the boot block section is locked out. when the device is in the soft- ware product identification mode (see software product identification entry and exit sections) a read from address location 00002h will show if programming the boot block is locked out. if the data on i/o0 is low, the boot block can be programmed; if the data on i/o0 is high, the program lock- out feature has been activated and the block cannot be data inputs/outputs i/o0 - i/o7 data latch input/output buffers y-gating main memory (248k bytes) optional boot block (8k bytes) oe, ce and we logic y decoder x decoder vcc gnd oe we ce address inputs 3ffff 02000 01fff 00000
at49f020 3 programmed. the software product identification code should be used to return to standard operation. product identification: the product identification mode identifies the device and manufacturer as atmel. it may be accessed by hardware or software operation. the hardware operation mode can be used by an external pro- grammer to identify the correct programming algorithm for the atmel product. for details, see operating modes (for hardware operation) or software product identification. the manufacturer and device code is the same for both modes. data polling: the at49f020 features data polling to indicate the end of a program cycle. during a program cycle an attempted read of the last byte loaded will result in the complement of the loaded data on i/o7. once the pro- gram cycle has been completed, true data is valid on all outputs and the next cycle may begin. data polling may begin at any time during the program cycle. toggle bit: in addition to data polling the at49f020 provides another method for determining the end of a pro- gram or erase cycle. during a program or erase operation, successive attempts to read data from the device will result in i/o6 toggling between one and zero. once the program cycle has completed, i/o6 will stop toggling and valid data will be read. examining the toggle bit may begin at any time during a program cycle. hardware data protection: hardware features protect against inadvertent programs to the at49f020 in the following ways: (a) v cc senseif v cc is below 3.8v (typical), the program function is inhibited; (b) program inhibitholding any one of oe low, ce high or we high inhibits program cycles; and (c) noise filterpulses of less than 15 ns (typical) on the we or ce inputs will not initiate a program cycle. notes: 1. the 8k byte boot sector has the address range 00000h to 01fffh. 2. either one of the product id exit commands can be used. command definition (in hex) command sequence bus cycles 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle 5th bus cycle 6th bus cycle addr data addr data addr data addr data addr data addr data read 1 addr d out chip erase 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 10 byte program 4 5555 aa 2aaa 55 5555 a0 addr d in boot block lockout (1) 6 5555 aa 2aaa 55 5555 80 5555 aa 2aaa 55 5555 40 product id entry 3 5555 aa 2aaa 55 5555 90 product id exit (2) 3 5555 aa 2aaa 55 5555 f0 product id exit (2) 1 xxxx f0 absolute maximum ratings* temperature under bias................................ -55 c to +125 c *notice: stresses beyond those listed under absolute maximum ratings may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature ..................................... -65 c to +150 c all input voltages (including nc pins) with respect to ground ...................................-0.6v to +6.25v all output voltages with respect to ground .............................-0.6v to v cc + 0.6v voltage on oe with respect to ground ...................................-0.6v to +13.5v
at49f020 4 notes: 1. x can be v il or v ih . 2. refer to ac programming waveforms. 3. v h = 12.0v 0.5v. 4. manufacturer code: 1fh, device code: 0bh. 5. see details under software product identification entry/exit. note: 1. in the erase mode, i cc is 90 ma. dc and ac operating range at49f020-90 at49f020-12 at49f020-15 operating temperature (case) com. 0c - 70c 0c - 70c 0c - 70c ind. -40c - 85c -40c - 85c -40c - 85c v cc power supply 5v 10% 5v 10% 5v 10% operating modes mode ce oe we ai i/o read v il v il v ih ai d out program (2) v il v ih v il ai d in standby/write inhibit v ih x (1) x x high z program inhibit x x v ih program inhibit x v il x output disable x v ih x high z product identification hardware v il v il v ih a1 - a17 = v il , a9 = v h , (3) a0 = v il manufacturer code (4) a1 - a17 = v il , a9 = v h , (3) a0 = v ih device code (4) software (5) a0 = v il , a1 - a17=v il manufacturer code (4) a0 = v ih , a1 - a17=v il device code (4) dc characteristics symbol parameter condition min max units i li input load current v in = 0v to v cc 10 m a i lo output leakage current v i/o = 0v to v cc 10 m a i sb1 v cc standby current cmos ce = v cc - 0.3v to v cc com. 100 m a ind. 300 m a i sb2 v cc standby current ttl ce = 2.0v to v cc 3ma i cc (1) v cc active current f = 5 mhz; i out = 0 ma 50 ma v il input low voltage 0.8 v v ih input high voltage 2.0 v v ol output low voltage i ol = 2.1 ma 0.45 v v oh1 output high voltage i oh = -400 m a2.4v v oh2 output high voltage cmos i oh = -100 m a; v cc = 4.5v 4.2 v
at49f020 5 ac read waveforms (1)(2)(3)(4) notes: 1. ce may be delayed up to t acc - t ce after the address transition without impact on t acc . 2. oe may be delayed up to t ce - t oe after the falling edge of ce without impact on t ce or by t acc - t oe after an address change without impact on t acc . 3. t df is specified from oe or ce whichever occurs first (cl = 5 pf). 4. this parameter is characterized and is not 100% tested. input test waveforms and measurement level output test load note: 1. this parameter is characterized and is not 100% tested. ac read characteristics symbol parameter at49f020-90 at49f020-12 at49f020-15 units minmaxminmaxminmax t acc address to output delay 90 120 150 ns t ce (1) ce to output delay 90 120 150 ns t oe (2) oe to output delay 0 40 0 50 0 70 ns t df (3)(4) ce or oe to output float 0 25 0 30 0 40 ns t oh output hold from oe , ce or address, whichever occurred first 000ns t r , t f < 5 ns pin capacitance f = 1 mhz, t = 25c (1) symbol typ max units conditions c in 46pfv in = 0v c out 812pfv out = 0v
at49f020 6 ac byte load waveforms we controlled ce controlled ac byte load characteristics symbol parameter min max units t as , t oes address, oe set-up time 0 ns t ah address hold time 50 ns t cs chip select set-up time 0 ns t ch chip select hold time 0 ns t wp write pulse width (we or ce )90ns t ds data set-up time 50 ns t dh , t oeh data, oe hold time 0 ns t wph write pulse width high 90 ns
at49f020 7 program cycle waveforms chip erase cycle waveforms note: 1. oe must be high only when we and ce are both low. program cycle characteristics symbol parameter min typ max units t bp byte programming time 10 50 m s t as address set-up time 0 ns t ah address hold time 50 ns t ds data set-up time 50 ns t dh data hold time 0 ns t wp write pulse width 90 ns t wph write pulse width high 90 ns t ec erase cycle time 10 seconds
at49f020 8 notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. data polling waveforms notes: 1. these parameters are characterized and not 100% tested. 2. see t oe spec in ac read characteristics. toggle bit waveforms (1)(2)(3) notes: 1. toggling either oe or ce or both oe and ce will operate toggle bit. the t oehp specification must be met by the toggling input(s). 2. beginning and ending state of i/o6 will vary. 3. any address location may be used but the address should not vary. data polling characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t wr write recovery time 0 ns toggle bit characteristics (1) symbol parameter min typ max units t dh data hold time 10 ns t oeh oe hold time 10 ns t oe oe to output delay (2) ns t oehp oe high pulse 150 ns t wr write recovery time 0 ns
at49f020 9 software product identification entry (1) software product identification exit (1) notes for software product identification: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. a1 - a17 = v il . manufacturer code is read for a0 = v il ; device code is read for a0 = v ih . 3. the device does not remain in identification mode if powered down. 4. the device returns to standard operation mode. 5. manufacturer code is 1fh. the device code is 0bh. boot block lockout feature enable algorithm (1) notes for boot block lockout feature enable: 1. data format: i/o7 - i/o0 (hex); address format: a14 - a0 (hex). 2. boot block lockout feature enabled. load data aa to address 5555 load data 55 to address 2aaa load data 90 to address 5555 enter product identification mode (2)(3)(5) load data aa to address 5555 load data 55 to address 2aaa load data f0 to address 5555 exit product identification mode (4) load data f0 to any address exit product identification mode (4) or pause 1 second (2) load data aa to address 5555 load data 55 to address 2aaa load data 80 to address 5555 load data aa to address 5555 load data 55 to address 2aaa load data 40 to address 5555
at49f020 10 note: 1. the at49f020 has an optional boot block feature. the part number shown in the ordering information table is for devices with the boot block in the lower address range (i.e., 00000h to 01fffh). users requiring the boot block to be in the higher address range should contact atmel. ordering information (1) t acc (ns) i cc (ma) ordering code package operation range active standby 90 50 0.1 at49f020-90jc at49f020-90pc at49f020-90tc 32j 32p6 32t commercial (0 to 70 c) 50 0.3 at49f020-90ji at49f020-90pi at49f020-90ti 32j 32p6 32t industrial (-40 to 85 c) 120 50 0.1 at49f020-12jc at49f020-12pc at49f020-12tc 32j 32p6 32t commercial (0 to 70 c) 50 0.3 at49f020-12ji at49f020-12pi at49f020-12ti 32j 32p6 32t industrial (-40 to 85 c) 150 50 0.1 at49f020-15jc at49f020-15pc AT49F020-15TC 32j 32p6 32t commercial (0 to 70 c) 50 0.3 at49f020-15ji at49f020-15pi at49f020-15ti 32j 32p6 32t industrial (-40 to 85 c) package type 32j 32-lead, plastic, j-leaded chip carrier package (plcc) 32p6 32-lead, 0.600" wide, plastic dual inline package (pdip) 32t 32-lead, thin small outline package (tsop)
at49f020 11 packaging information .045(1.14) x 45? pin no. 1 identify .025(.635) x 30? - 45? .012(.305) .008(.203) .021(.533) .013(.330) .530(13.5) .490(12.4) .030(.762) .015(.381) .095(2.41) .060(1.52) .140(3.56) .120(3.05) .032(.813) .026(.660) .050(1.27) typ .553(14.0) .547(13.9) .595(15.1) .585(14.9) .300(7.62) ref .430(10.9) .390(9.90) at contact points .022(.559) x 45? max (3x) .453(11.5) .447(11.4) .495(12.6) .485(12.3) 1.67(42.4) 1.64(41.7) pin 1 .566(14.4) .530(13.5) .090(2.29) max .005(.127) min .065(1.65) .015(.381) .022(.559) .014(.356) .065(1.65) .041(1.04) .630(16.0) .590(15.0) 0 15 ref .690(17.5) .610(15.5) .012(.305) .008(.203) .110(2.79) .090(2.29) .161(4.09) .125(3.18) seating plane .220(5.59) max 1.500(38.10) ref *controlling dimension: millimeters index mark 18.5(.728) 18.3(.720) 20.2(.795) 19.8(.780) 0.25(.010) 0.15(.006) 0.50(.020) bsc 7.50(.295) ref 8.20(.323) 7.80(.307) 1.20(.047) max 0.15(.006) 0.05(.002) 0 5 ref 0.70(.028) 0.50(.020) 0.20(.008) 0.10(.004) 32j , 32-lead, plastic j-leaded chip carrier (plcc) dimensions in inches and (millimeters) jedec outline ms-016 ae 32p6 , 32-lead, 0.600" wide, plastic dual inline package (pdip) dimensions in inches and (millimeters) 32t , 32-lead, plastic thin small outline package (tsop) dimensions in millimeters and (inches)* jedec outline mo-142 bd
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